1. Field
Exemplary embodiments of the present invention relate to a semiconductor designing technology, and more particularly, to a semiconductor memory device having a stacked structure and a method for driving the semiconductor memory device.
2. Description of the Related Art
The development of packing technology has resulted in smaller sizes in semiconductor devices and improved packaging reliability. As high performance is also desired, further developments in stacked packages have developed.
A “stack” is at least two semiconductor chips or packages vertically piled in a semiconductor device. For example, when the stacked package is applied to a semiconductor memory device, such as a Dynamic Random Access Memory (DRAM) device, the semiconductor memory device may have a memory capacity of more than twice a memory capacity of an integrated semiconductor without stacked packages. Also, since the stacked package is advantageous in terms of packaging density and packaging area in addition to the increase in memory capacity, research and development on the stacked package are being accelerated.
There are two methods for fabricating a stacked package. The first method stacks individual semiconductor chips and subsequently packages the stacked semiconductor chips all at once, and the second method stacks packaged individual semiconductor chips. The individual semiconductor chips of a stacked package are electrically connected through a metal wire or by chip through vias. Specifically, in a stacked package using chip through vias, semiconductor chips are physically and electrically connected with each other in a vertical direction through the chip through vias that are formed in the inside of the semiconductor chips.
Additionally, among the semiconductor chips included in a stacked package, a semiconductor chip that is coupled with an external device and receives and transfers power and data is referred to as a master chip, and a semiconductor chip that stores and provides data under the control of the master chip is referred to as a slave chip. In particular, technology that includes, for example, only a core region in a slave chip is being developed to minimize the size of the slave chip.
FIG. 1 illustrates an internal structure of a slave chip included in a semiconductor memory device according to a prior art.
Referring to FIG. 1, the slave chip includes a plurality of banks BANK0 to BANK7 for storing and providing data, and a plurality of first global input/output lines GIO1 and a plurality of second global input/output lines GIO2 for inputting/outputting data between the banks BANK0 to BANK7 and a master chip (not shown).
The banks BANK0 to BANK7 are respectively divided corresponding to a first data pad group UDQ and a second data pad group LDQ, and a first group of banks BANK0, BANK1, BANK4 and BANK5 share the first global input/output lines GIO1, and a second group of banks BANK2, BANK3, BANK6 and BANK7 share the second global input/output lines GIO2.
For example, when a slave chip has a density of approximately 1 G bits and includes eight banks, each bank has a density of approximately 128M bits. In other words, each half bank has a density of approximately 64M bits. More specifically, the first data pad group UDQ and the second data pad group LDQ each have a density of approximately 64M bits. Therefore, the slave chip includes a memory cell corresponding to approximately 128M bits for each bank and approximately 128 global input/output lines GIO1 and GIO2.
The slave chip having the above structure requires the number of the global input/output lines GIO11 or GIO12 corresponding to the number of memory cells, the area of the slave chip shown in FIG. 1 maybe increased. Further, since the slave chip has a structure of sharing the global input/output lines GIO11 or GIO12 for some banks BANK0, BANK1, BANK4 and BANK5 or BANK2, BANK3, BANK6 and BANK7, line loading of the global input/output lines GIO11 and GIO12 may increase.